This invention relates to integrated circuits, and more particularly, to selectively forming serializer-deserializer circuitry from registers in input-output circuits on an integrated circuit.
Integrated circuits are often used to handle both single-ended and differential data signals. Single-ended signals are referenced to ground. In differential data signals, the voltages on a pair of lines are referenced to each other. Differential data signaling schemes such as the well-known low-voltage differential signaling (LVDS) scheme are commonly used to handle signals in the GHz frequency range. The use of differential data signaling schemes can help system designers to overcome noise problems. Single-ended data signaling schemes tend to be used at lower data rates, where noise immunity is less of an issue.
Integrated circuits that contain differential communications circuitry typically contain serializer-deserializer circuitry. This circuitry, which is sometimes referred to as SERDES circuitry, is used to convert high-speed incoming serial data streams into lower-speed parallel data streams. SERDES circuitry is also used to convert parallel data to serial data prior to data transmission to another integrated circuit using a differential output driver. SERDES circuitry includes shift registers that are formed from a number of individual data registers.
In serial-to-parallel operation (e.g., when incoming serial data is being processed), serial data is clocked into the shift register in a SERDES circuit using a high speed serial clock. Once the shift register is full, the data is shifted out of the shift register in parallel using a lower-speed parallel clock.
In parallel-to-serial operation (e.g., when transmitting serial data), bits of parallel data are shifted into the shift register in parallel using the parallel clock. A corresponding serialized data stream is then provided at the serial output of the shift register at the serial clock rate.
In conventional integrated circuits, the shift registers in SERDES circuit blocks are hardwired. This type of arrangement may provide acceptable serial-to-parallel and parallel-to-serial data conversion performance, but can be inefficient. For example, if the SERDES capabilities of the integrated circuit are not used by a logic designer, the resources used by the shift register are wasted and represent needless overhead.
In certain types of integrated circuits such as programmable logic devices, it may be possible to use general purpose programmable logic resources such as logic element register resources to selectively implement serializer-deserializer circuitry. This type of arrangement may provide design flexibility, but can limit performance due to routing delays. This type of arrangement may also have high implementation costs and can reduce the amount of programmable circuitry that would otherwise be available to implement a user's custom logic design.
It would therefore be desirable to provide integrated circuits in which serial-deserializer circuitry may be selectively formed from available register resources.